1. Field of the Invention
The present invention relates to a semiconductor device fabrication process, more particularly to the formation of alignment marks in the fabrication of, for example, silicon-on-insulator semiconductor devices.
2. Description of the Related Art
Semiconductor device fabrication processes typically include many photolithographic steps in which a film deposited on a semiconductor wafer is patterned to form elements of an integrated circuit. In these steps, the desired circuit pattern is first transferred to a photoresist by exposing the photoresist to light through a photomask and developing the photoresist. The photoresist then serves as an etching mask through which the film is etched in the desired pattern.
The photomask may be a glass plate on which the circuit pattern is defined with a material such as chrome that blocks light of the wavelength to which the photoresist will be exposed. An image of the circuit pattern may be formed on the photoresist by a reflective or transmissive optical scheme, with or without a reduction in size.
During the exposure process, it is essential for the photomask to be correctly aligned with the semiconductor wafer. One method of alignment is to position the wafer so that marks formed on the photomask and wafer are mutually aligned. The alignment marks formed on the wafer may be concave pits or trenches, convex mesas, or more complex relief patterns; such alignment marks can be detected from light reflected or diffracted from their edges.
Recently there has been much interest in silicon-on-insulator (SOI) semiconductor devices, in which transistors and other circuit elements are formed in a thin silicon semiconductor layer overlying an insulator layer in a semiconductor wafer. The thin semiconductor layer is divided into isolated active regions by a process such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI). SOI devices can operate at high speed with low power consumption because the parasitic capacitance and junction leakage of their circuit elements is reduced. As ever higher levels of functionality and performance are required, the gate lengths of the transistors in SOI devices have been reduced to the point where it is necessary to form the transistors in a very thin semiconductor layer in order to suppress short channel effects.
This leads to alignment problems, however, because the step height of alignment marks formed in a very thin semiconductor layer is too small for adequate reflection or diffraction, making accurate detection of the alignment marks difficult.
U.S. Pat. No. 6,368,936 discloses a method of forming a semiconductor integrated circuit of the SOI type in which the alignment marks penetrate through the insulator layer as well as through the thin semiconductor layer. The alignment marks are formed in a separate process preceding local oxidation of silicon. Extra photolithography, etching, and alignment steps are therefore required.
U.S. Pat. No. 6,673,635 discloses another method of forming an SOI semiconductor integrated circuit in which the alignment marks penetrate the insulator layer, but the alignment marks are confined to the lower part of the insulator layer, and cannot take full advantage of the combined thickness of the semiconductor and insulator layers. In addition, although the alignment marks are formed during a conventional trench isolation process, this process must be preceded by a separate process that selectively etches the semiconductor layer and the upper part of the insulator layer.
U.S. Pat. No. 5,369,050 discloses a method of forming an SOI semiconductor integrated circuit in which convex alignment marks are surrounded by grooves that enhance their visibility, but the formation of the grooves also requires a separate process.
It would be desirable to have a method of forming alignment marks in a semiconductor integrated circuit of the SOI type that required a minimum of extra process steps.